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Serial peripheral interface (SPI)
Procedure
RM0008
1.
2.
3.
4.
5.
6.
Select the BR[2:0] bits to define the serial clock baud rate (see SPI_CR1 register).
Select the CPOL and CPHA bits to define one of the four relationships between the
data transfer and the serial clock (see Figure 210 ).
Set the DFF bit to define 8- or 16-bit data frame format
Configure the LSBFIRST bit in the SPI_CR1 register to define the frame format
If the NSS pin is required in input mode, in hardware mode, connect the NSS pin to a
high-level signal during the complete byte transmit sequence. In software mode, set the
SSM and SSI bits in the SPI_CR1 register.
If the NSS pin is required in output mode, the SSOE bit only should be set.
The MSTR and SPE bits must be set (they remain set only if the NSS pin is connected
to a high-level signal).
In this configuration the MOSI pin is a data output and the MISO pin is a data input.
Transmit sequence
The transmit sequence begins when a byte is written in the Tx Buffer.
The data byte is parallel-loaded into the shift register (from the internal bus) during the first
bit transmission and then shifted out serially to the MOSI pin MSB first or LSB first
depending on the LSBFIRST bit in the SPI_CR1 register. The TXE flag is set on the transfer
of data from the Tx Buffer to the shift register and an interrupt is generated if the TXEIE bit in
the SPI_CR2 register is set.
Receive sequence
For the receiver, when data transfer is complete:
●
●
The data in the shift register is transferred to the RX Buffer and the RXNE flag is set
An interrupt is generated if the RXNEIE bit is set in the SPI_CR2 register
At the last sampling clock edge the RXNE bit is set, a copy of the data byte received in the
shift register is moved to the Rx buffer. When the SPI_DR register is read, the SPI
peripheral returns this buffered value.
Clearing the RXNE bit is performed by reading the SPI_DR register.
A continuous transmit stream can be maintained if the next data to be transmitted is put in
the Tx buffer once the transmission is started. Note that TXE flag should be ‘1’ before any
attempt to write the Tx buffer is made.
Note:
23.3.4
In the NSS hardware mode, the slave's NSS input is controlled by the NSS pin or another
GPIO pin that has to be controlled by software.
Simplex communication
The SPI is capable of operating in simplex mode in 2 configurations.
●
●
1 clock and 1 bidirectional data wire
1 clock and 1 data wire (receive-only in full-duplex mode)
1 clock and 1 bidirectional data wire
This mode is enabled by setting the BIDIMODE bit in the SPI_CR1 register. In this mode
SCK is used for the clock and MOSI in master or MISO in slave mode is used for data
594/995
Doc ID 13902 Rev 9
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